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[VHDL-FPGA-Verilog] cpu16

Description: 16位cpu设计vhdl源码。主要实现risc机器模型-16-bit cpu design code
Platform: | Size: 182272 | Author: peterloo | Hits:

[VHDL-FPGA-Verilog] cpu-design

Description: VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
Platform: | Size: 2879488 | Author: lzy | Hits:

[VHDL-FPGA-Verilog] risc5x_latest.tar

Description: risc processor vhdl code and it is very useful
Platform: | Size: 257024 | Author: k | Hits:

[VHDL-FPGA-Verilog] RISC8

Description: 设计一台 8 位的 RISC 模型机，要求具有以下验证程序所要求的功能： 求出 1 到任意一个整数 N 之间的所有偶数之和并输出显示，和为单字长。说明：N 从开 关输入，和从数码管输出，然后输出显示停止。--risc8 bit microprocessor vhdl source code. Processing functions: find an integer N between 1 and any odd sum. And output.
Platform: | Size: 1868800 | Author: 韦乃华 | Hits:

[VHDL-FPGA-Verilog] 65905857-A-A

Description: vhdl code for risc processor-vhdl code for risc processor...........................
Platform: | Size: 10240 | Author: satya | Hits:

[ARM-PowerPC-ColdFire-MIPS] mrsic_test_bench

Description: its about risc processor in vhdl
Platform: | Size: 1024 | Author: ashu | Hits:

[Other] vhdl2

Description: Vhdl dili kullanilmistir. kaynak turkcedir. risc mimarisi kullanilmistir
Platform: | Size: 4727808 | Author: nusret | Hits:

[VHDL-FPGA-Verilog] 8Bit-CPU

Description: 8 Bit RISC CPU implementation in VHDL
Platform: | Size: 5120 | Author: Mufossa | Hits:

[source in ebook] ddca2e-hdl

Description: vhdl mips risc computer architecture-vhdl mips risc
Platform: | Size: 38912 | Author: hf | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
Platform: | Size: 822272 | Author: wang | Hits:

[Software Engineering] CPU

Description: 我是2014级复旦的研究生。这是一个8位的CPU设计VHDL实现。本CPU基于RISC架构，实现了cpu的基本功能如：加减乘除运算，跳转等。此外，里面有一个17位的ROM区，是存储指令的。你可以写出一段17位的指令代码，并放入ROM区，该CPU即可自动运行出结果。压缩包里是源代码和我们当时的设计要求。本源代码的最后调试时在地址0 17是放入的斐波纳契数字(Fibonacci Numbers)指令。通过modelsim仿真即可看到结果。-I am a 2014 graduate of Fudan University. This is an 8-bit CPU design VHDL implementation. The CPU based on RISC architecture to achieve the basic functions, such as cpu: arithmetic operations, jumps and so on. In addition, there are a ROM area 17, is stored in the instruction. You can write some 17 of the instruction code, and placed in the ROM area, the CPU will automatically run the result. Compression bag is the source code and design requirements of our time. When the final commissioning source code is placed in the address 0 17 of Fibonacci numbers (Fibonacci Numbers) instruction. You can see the results of the simulation by modelsim.
Platform: | Size: 520192 | Author: ljt | Hits:

[VHDL-FPGA-Verilog] f32c-master

Description: FPGArduino源码，f32c：VHDL的MIPS和RISC-V指令集实现(FPGArduino source code, f32c:VHDL MIPS and RISC-V instruction set implementation)
Platform: | Size: 3957760 | Author: Peter Bee | Hits:
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